A Fast Reactivation Scheme in Power Gating Design

Abstract:

Power gating has become a popular technique to reduce the ever-increasing leakage power for commercial microprocessors or SoCs, however the wakeup energy and delay cost harm its performance. This paper proposes a fast reactivation scheme to reduce the transition delay and energy. The experiment results show that, comparing to the traditional power gating implementation, it can achieve 19.66% reactivation energy reduction, 9.28% peak leakage reduction, and 23.36% wakeup delay reduction, at the cost of 2.75% area increasing.

• Periodical: Applied Mechanics and Materials (Volumes 135-136)
• Pages: 1134-1139
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.135-136.1134
• Online since: October 2011
• Authors: Ping Huang, Hui Yuan Xing, Xian Ju Yang, Pei Xiang Yan, Tian Lei Zhao, Zuo Cheng Xing
• Keywords: Charge Recycling, Low-Power Design, Power Gating, VLSI

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