Design of the 16-bit ADC Using FPGA

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Abstract:

There are many kinds of ADC chips which are analog or analog-digital mixed at home and abroad. It can not be integrated into a pure digital chip, in this paper, a way to realize quasi-digital 16- bit ADC based on stochastic logic was given. Except few analog elements, all are digital circuits. The paper describes the design principle and presents the simulation and hardware test results based on FPGA chips produced by Altera show that the shortest conversion time can reach 0.8ms. The hardware test shows that the design is successful.

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92-96

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December 2011

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© 2012 Trans Tech Publications Ltd. All Rights Reserved

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[1] Antonio J. Ascota, Adoracion Rueda and Jose L. Huertas, A VHDl-based Methodology for the Design and Verification of Pipeline A/D Converters, Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pp.534-538, March (2000).

DOI: 10.1109/date.2000.840837

Google Scholar

[2] Buenzli. C, Owen. L, Rose. F, Hardware/Software Codesign of a Scalable Embedded Radar Signal Processor", VHDL International Users, Forum, pp.200-208, Oct. (1997).

DOI: 10.1109/viuf.1997.623951

Google Scholar

[3] Chun-Chi Chen, Poki Chen, Chorng-Sii Hwang, Wei Chang, A Precise Cyclic CMOS Time-to-Digital Converter With Low Thermal Sensitivity, IEEE Transactions on Nuclear Science, VOL. 52, NO. 4, pp.834-838, August (2005).

DOI: 10.1109/tns.2005.852708

Google Scholar

[4] Information on http: / www. altera. com. cn.

Google Scholar

[5] Ortega C.L. Janer J.M. Quero and L.G. Franquelo,J. Pinilla and J. Serrano, Analog to Digital and Digital to Analog Conversion Based on Stochastic Logic", IEEE Intl. Conf. on Ind. Electr. IECON, 95, Orlando, Nov. (1995).

DOI: 10.1109/iecon.1995.483865

Google Scholar