A Robust SRAM Design for Ultra Dynamic Voltage Scalable VLSI System

Abstract:

In this paper, a SRAM array targeting IBM 130nm CMOS technology is proposed for ultra dynamic voltage scaling (UDVS) application with better immunity against process variation. A type of modified Schmitt Trigger inverter is adopted in the SRAM design, which guarantee stable operations in both superthreshold and subthreshold supply voltage regions. Testing results demonstrate that the proposed SRAM array functions well in the supply voltage range of 150 mV to 1200 mV. The optimum-energy supply voltage point is about 400 mV for proposed UDVS SRAM array. And the energy at 400 mV decreases by 62.5% compared to that at 1200 mV.

• Periodical: Applied Mechanics and Materials (Volumes 182-183)
• Pages: 450-455
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.182-183.450
• Online since: June 2012
• Authors: Jun Yang, Na Bai, Wei Qi Wu, Wei Wei Shan, Zhi Kuang Cai
• Keywords: Low Power, Process Variation, Sense Amplifier, Static Noise Margin (SNM), Ultra Dynamic Voltage Scalable (UDVS) SRAM

References

[1] L. Yu-Huei, et al., A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System, Solid-State Circuits, IEEE Journal of, vol. 45, pp.2227-2238, (2010).

DOI: 10.1109/mssc.2010.936624

[2] Z. Chen and M. Dongsheng, A 10-MHz Green-Mode Automatic Reconfigurable Switching Converter for DVS-Enabled VLSI Systems, Solid-State Circuits, IEEE Journal of, vol. 46, pp.1464-1477, (2011).

DOI: 10.1109/jssc.2011.2131770

[3] B. H. Calhoun, et al., Flexible Circuits and Architectures for Ultralow Power, Proceedings of the IEEE, vol. 98, pp.267-282, (2010).

[4] B. H. Calhoun, et al, Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering, IEEE Journal of Solid-state Circuits, vol. 41, pp.238-245, (2006).

DOI: 10.1109/jssc.2005.859886

[5] H. Myeong-Eun and K. Roy, ABRM: Adaptive β-Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling , Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 18, pp.281-290, (2010).

DOI: 10.1109/tvlsi.2008.2010767

[6] C. Meng-Fan, et al., A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications, Solid-State Circuits, IEEE Journal of, vol. 46, pp.520-529, (2011).

DOI: 10.1109/jssc.2010.2091321

[7] F. Moradi, et al., Process variations in sub-threshold SRAM cells in 65nm CMOS, in Microelectronics (ICM), 2010 International Conference on, pp.371-374, (2010).

DOI: 10.1109/icm.2010.5696164

[8] L. Chang, et al., Stable SRAM cell design for the 32 nm node and beyond, in proceedings of Symposium of VLSI Technology, pp.128-129, (2005).

[9] J. Chen, L. T. Clark, and T. Chen, An ultra-low-power memory with a subthreshold power supply voltage, IEEE Journal of Solid-State Circuits, vol. 41, no. 10, p.2344–2353, (2006).

DOI: 10.1109/jssc.2006.881549

[10] N. Verma and A.P. Chandrakasan, A 256 kb 65nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy, IEEE Journal of Solid-State Circuits, vol. 43,  no. 1,  pp.141-149, (2008).

DOI: 10.1109/jssc.2007.908005

[11] T.H. Kim, J. Liu, J. Keane, and C.H. Kim, A 0. 2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing, , IEEE Journal of Solid-State Circuits, vol. 43,  no. 2,  pp.518-529, (2008).

DOI: 10.1109/jssc.2007.914328

[12] T.H. Kim, J. Liu, J. Keane, and C.H. Kim, A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme, in proceedings of IEEE International Solid-State Circuits Conference, pp.330-606, (2007).

DOI: 10.1109/isscc.2007.373428

[13] J.P. Kulkarni, K. Kim, K. Roy, A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM, IEEE Journal of Solid-State Circuits, vol. 42, no. 10, pp.2303-2313, (2007).

DOI: 10.1109/jssc.2007.897148