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Ultra-Low Power Static Logic Circuits Design in Subthreshold Region
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Ultra-Low Power Static Logic Circuits Design in Subthreshold Region

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Abstract:

As semiconductor technology develops toward very deep submicron or even nanometer, power consumption per unit area increases dramatically. Scaling supply voltage into the subthreshold region provides significant energy reduction in logic circuits. However, low voltage and varies of environmental factors make it a challenge to design subthreshold circuit. This paper presents a method to modify standard cells to function well in subthreshold region. The main factors including process, voltage and temperature variables, noise and mismatch, which have more influence on the performance in the sub-threshold region than the strong inversion region. Typical static logics in the standard library TSMC65nm are analyzed by Monte Carlo analysis method when working in sub-threshold region, to find that logical failures occur to NAND VOL and NOR VOH before modified the sizes. After NAND's size increasing 85% and NOR's 370%, the failure has been eliminated and a good noise margin has been achieved.

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Periodical:

Applied Mechanics and Materials (Volumes 182-183)

Pages:

467-471

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.182-183.467

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Online since:

June 2012

Authors:

Jie Li, Zhuang Zhang, Wei Wei Shan

Keywords:

Low Power, Static Logic Circuits, Subthreshold

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© 2012 Trans Tech Publications Ltd. All Rights Reserved

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