[1]
S. Jiang , M. A. Do and K. S. Yeo "A 200-MHz CMOS mixed-mode sample-and-hold circuit for pipelined ADCs", Proc. IFIP Int. Conf. Very Large-Scale Integr., p.352 (2006)
DOI: 10.1109/vlsisoc.2006.313260
Google Scholar
[2]
B. Razavi, Principles of Data Conversion System Design. New York: IEEE press, 1995.
Google Scholar
[3]
A. Boni, A. Pierazzi and C. Morandi, "A-10-b 185 MS/s track-and-hold in 0,35-μm CMOS," IEEE J. Solid-State Circuit, vol. 36, no. 2, pp.195-203, Feb. 2001.
DOI: 10.1109/4.902760
Google Scholar
[4]
J. Lim and B. A. Wooly, "A High Speed Sample-and-Hold Technique using a Miller Hold Capacitance," IEEE J. Solid-State Circuits, vol. 26, No. 4, pp.643-651, April 1991.
DOI: 10.1109/4.75067
Google Scholar
[5]
Lei Wang, Junyan Ren, Wenjing Yin, Tingqian Chen, Jun Xu, "A High-Speed High-Resolution Low-Distortion CMOS Bootstrapped Switch", IEEE ISCAS 2007, pp.1721-1724 May, 2007.
DOI: 10.1109/iscas.2007.377926
Google Scholar
[6]
D. B. Estreich, The physics and modeling of latch-up and CMOS integrated circuits, (1980)
Google Scholar
[7]
Kontos, D., Gauthier, R., Chatty, K., Domanskr, K., Muhammad, M., Seguin, C., Halbach, R., "External Latchup Characteristics Under Static and Transient Conditions in Advanced Bulk CMOS Technologies", Reliability physics symposium, 2007. proceedings. 45th annual. ieee international, On page(s): 358 - 363, Volume: Issue: , 15-19 April (2007)
DOI: 10.1109/relphy.2007.369915
Google Scholar
[8]
M. Hargrove, S. Voldman, R. Gauthier, 1. Brown, K. Duncan, and W. Craig, "Latchup in CMOS technology, " in Proc. IEEE Int. Reliab . Phys. Symp., 1998. pp.269-78.
DOI: 10.1109/relphy.1998.670561
Google Scholar
[9]
M.-D. Ker and S.-F. Hsu, "Physical mechanism and device simulation on transient-induced latchup in CMOS ICs under system-level ESD test, " IEEE Trans. Electron Devices, vol. 52, no. 8, pp.1821-1831, 2005.
DOI: 10.1109/ted.2005.852728
Google Scholar
[10]
N. Li, et al "High efficiency four-phase all PMOS charge pump without body effects," International Conference on Communications, Circuits and Systems, pp.1083-1087, 2008.
DOI: 10.1109/icccas.2008.4657956
Google Scholar
[11]
Raben, H., Borg, J., Johansson, J., "Improved efficiency in the CMOS cross-connected bridge rectifier for RFID applications", Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, On page(s): 334 - 339, Volume: Issue: , 16-18 June (2011)
DOI: 10.1109/mixdes.2016.7529757
Google Scholar
[12]
K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, and R. G. Renninger, "A 250-mW 8-b 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers", IEEE J. Solid-State Circuits, vol. 32, pp.312-320, Mar. 1997.
DOI: 10.1109/4.557628
Google Scholar
[13]
Behzad Razavi, "Design of Analog CMOS Integrated Circuits", the McGraw-Hill Companies, Inc., 2001.Ppp.384-390.
Google Scholar
[14]
G. Erdi, "Amplifier techniques for combining low noise, precision, and high-speed performance",IEEE J. Solid-State Circuits, vol. SC-16, pp.653-661, Dec. (1981)
DOI: 10.1109/jssc.1981.1051658
Google Scholar