Test Method for Crosstalk Faults in VLSI Circuits Based on Multiple-Valued Decision Diagrams

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The crosstalk fault in VLSI circuits is one of the interference effects being caused by parasitic capacitance and inductance coupling, it can lead to functional errors of circuits. It is necessary to detect the crosstalk faults in order to insure the functions of circuits. A new test method for crosstalk faults in VLSI circuits based on multiple-valued decision diagrams is presented in this paper, the test vectors of crosstalk faults are generated by building a multiple-valued decision diagram that is a difference operation of the two multiple-valued decision diagrams corresponding to the normal circuit and faulty circuit, respectively. One advantage of the test method is that it can get all test vectors of a given crosstalk fault, therefore for a digital circuit, the test set with minimal number of test vectors can be obtained. Experimental results on a lot of digital circuits demonstrate the feasibility of the method proposed in this paper.

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641-646

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January 2010

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© 2010 Trans Tech Publications Ltd. All Rights Reserved

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[1] B. Kaushik, S. Sarkar. Crosstalk analysis for a CMOS-gate-driven coupled interconnects. IEEE Trans. on CAD, vol. 27, no. 6, pp.1150-1154, (2008).

DOI: 10.1109/tcad.2008.923259

Google Scholar

[2] F. Mbairi, W. Siebert, H. Hesselbom. High-frequency transmission lines crosstalk reduction using spacing rules. IEEE Trans. on Components and Packaging Technologies, vol. 31, no. 3, pp.601-610, (2008).

DOI: 10.1109/tcapt.2008.2001163

Google Scholar

[3] S. Jaehoon, H. Juhee, Y. Hyunbean, J. Taejin, P. Sungju. Highly compact interconnect test patterns for crosstalk and static faults. IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 56, no. 5, pp.419-423, (2009).

DOI: 10.1109/tcsii.2009.2022373

Google Scholar

[4] L. Jianxun, W. Jone, S. Das. Crosstalk test pattern generation for dynamic programmable logic arrays. IEEE Trans. on Instrumentation and Measurement, vol. 55, no. 4, pp.1288-1302, (2006).

DOI: 10.1109/tim.2006.877721

Google Scholar

[5] Aniket, R. Arunachalam. A novel algorithm for testing crosstalk induced delay faults in VLSI circuits. 18th International Conference on VLSI Design, pp.479-484, (2005).

DOI: 10.1109/icvd.2005.125

Google Scholar

[6] B. Xiaoliang, S. Dey, J. Rajski. Self-test methodology for at-speed test of crosstalk in chip interconnects. 37th Design Automation Conference, pp.619-624, (2000).

DOI: 10.1145/337292.337597

Google Scholar

[7] W. Assadi, S. Kakarla. A BIST Technique for crosstalk noise detection in FPGAs. IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, pp.167-175, (2008).

DOI: 10.1109/dft.2008.14

Google Scholar

[8] R. Ebendt, W. Gunther, R. Drechsler. Combining ordered best-first search with branch and bound for exact BDD minimization. IEEE Trans. on CAD, vol. 24, no. 10, pp.1515-1529, (2005).

DOI: 10.1109/tcad.2005.852053

Google Scholar

[9] G. Fey, R. Drechsler. Minimizing the number of paths in BDDs: theory and algorithm. IEEE Trans. on CAD, vol. 25, no. 1, pp.4-11, (2006).

DOI: 10.1109/tcad.2005.852662

Google Scholar

[10] O. Keren. Reduction of average path length in binary decision diagrams by spectral methods. IEEE Trans. on Computer, vol. 57, no. 4, pp.520-531, (2008).

DOI: 10.1109/tc.2007.70811

Google Scholar

[11] J. Butler, T. Sasao, M. Matsuura. Average path length of binary decision diagrams. IEEE Trans. on Computer, vol. 54, no. 9, pp.1041-1053, (2005).

DOI: 10.1109/tc.2005.137

Google Scholar

[12] R. Ebendt, R. Drechsler. Exact minimisation of path-related objective functions for binary decision diagrams. IEE Proceedings on Computers and Digital Techniques, vol. 153, no. 4, pp.231-242, (2006).

DOI: 10.1049/ip-cdt:20050181

Google Scholar

[13] H. Babu, T. Sasao. Heuristics to minimize multiple-valued decision diagrams. IEICE Trans. Fundamental, vol. E83A, no. 12, pp.2498-2504, (2000).

Google Scholar

[14] C. Files, M. Nodine. MDD with added null-value and all-value edges. 38th International Symposium on Multiple-Valued Logic, pp.64-69, (2008).

DOI: 10.1109/ismvl.2008.20

Google Scholar