Design and Analysis of Low Power CNTFET TSPC D - Flip Flop Based Shift Registers
This paper enumerates the efficient design and analysis of low power CNTFET True single phase clock logic D Flip flop based shift registers. The TSPC D flip flop and shift registers are designed using Stanford University CNTFET model and proposed 10nm CNTFET model with sleepy keeper low power technique. The CNTFET is emerging as a viable replacement to the MOSFET. The transient and power analyses are obtained with operating voltage of 1V and the operating frequency at 1GHz. The simulation results are obtained and the analysis are compared with circuits designed using 32nm MOSFET. The comparison results are indicated that the proposed 10nm CNTFET based design and the low power technique are more efficient in power saving as compared to MOSFET design.
T. Ravi and V. Kannan, "Design and Analysis of Low Power CNTFET TSPC D - Flip Flop Based Shift Registers", Applied Mechanics and Materials, Vols. 229-231, pp. 1651-1655, 2012