The Reliability of Solder Joints in Fine Pitch 3-D Stack Package by Taguchi Method

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To achieve high density and high performance, through-Silicon Vias (TSVs) have recently aroused much interest because it is a key enabling technology for three-dimensional (3-D) integrated circuit stacking and silicon interposer technology. In this study, a 3-D 1/8th symmetrical nonlinear finite element model of a stack die TSV package was developed using ANSYS finite element simulation. The model was used to optimize the package for robust design and to determine design rules to enhance 3-D stack package in view of bump reliability. An L8(2×7) Taguchi matrix was developed to investigate the effects of interposer thickness, TSV diameter, insulation (SiO2) thickness, chip thickness, substrate thickness, bump height, and bump diameter on bumps reliability. A temperature cycling test in the range of 0 °C to 100 °C was conducted by three cycles. The mechanical property of SAC leadless solder included time independent plastic and time dependent creep behaviors. The parameter of inelastic strain range of the third cycle was used to evaluate the bump life prediction. Two levels were chosen for each parameter to cover the ranges of interest. The results show that the smaller insulation (SiO2) and substrate thickness and the larger dimension for the other factors provide the best combination. These could be used as guides for further similar 3-D stack packages design.

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Edited by:

Mohamed Othman

Pages:

434-439

Citation:

C. I. Chen et al., "The Reliability of Solder Joints in Fine Pitch 3-D Stack Package by Taguchi Method", Applied Mechanics and Materials, Vols. 229-231, pp. 434-439, 2012

Online since:

November 2012

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$38.00

[1] M. Koyanagi, H. Kurino, K.W. Lee, K. Sakuma, N. Miyakawa, H. Itani, Future System-on-Silicon LSI Chip, IEEE Micro, Vol. 18, No, 4, (1988), pp.17-22.

DOI: https://doi.org/10.1109/40.710867

[2] L. C. Shen, C. W. Chien, H. C. Cheng, C. T. Lin, Development of Three-dimensional Chip Stacking Technology Using a Clamped Through-silicon via Interconnection, Microelectronics Reliability, 50, Issue 4, (2010), pp.489-497.

DOI: https://doi.org/10.1016/j.microrel.2009.10.012

[3] E. K. Kim, Assessment of ultra-thin Si wafer thickness in 3D wafer stacking , Microelectronics Reliability, 50, Issue 2, (2010). pp.195-198.

DOI: https://doi.org/10.1016/j.microrel.2009.10.002

[4] Ching-I Chen, Fu-Chen Cheng, Chau-Jie Zhan and Tao-Chih Chang, Parameter Study to the interposer Stress Analysis of Fine Pitch 3-D Stack Package, The 5th International Microsystems, Packaging, Assembly and Circuits Technology Conference, Taipei, Taiwan, October 20-22, (2010).

DOI: https://doi.org/10.1109/impact.2010.5699608

[5] S. W. Yoon, D. W. Yang, J. H. Koo, M. Padmanathan and F. Carsom, 3D TSV Processes and its Assembly/Packaging Technology, IEEE International Conference on 3D System Integration, (2009), pp.1-5.

DOI: https://doi.org/10.1109/3dic.2009.5306535

[6] T. Chidambaram, C. McDonough, R. Geer, W. Wang, TSV Stress Testing and Modeling for 3D IC Applications, 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, (2009), pp, 727-730.

DOI: https://doi.org/10.1109/ipfa.2009.5232736

[7] H. Kitada, N. Maeda, K. Fujimoto, K. Suzuki, A. Kawai, K. Arai, T. Suzuki, T. Nakamura and T. Ohba, Stress Sensitivity Analysis on TSV Structure of Wafer-on-a-Wafer (WOW) by the Finite Element Method (FEM), IEEE International Interconnect Technology Conference, IITC, (2009).

DOI: https://doi.org/10.1109/iitc.2009.5090354

[8] C. S. Selvanayagam, J.H. Lau, X. Zhang, S. K. W. Seah, K. Vaidyanathan and T. C. Chai, Nonlinear Thermal Stress/ Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps, IEEE Transactions on Advanced Packaging , Vol. 32, No. 4, (2009).

DOI: https://doi.org/10.1109/tadvp.2009.2021661

[9] C. Noritake, P. Limaye, M. Gonzalez and Bart Vandevelde, Thermal Cycle Reliability of 3D Chip Stacked Package Using Pb-free Solder Bumps: Parameter Study by FEM Analysis, 7th. Int. Conf: on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE (2006).

DOI: https://doi.org/10.1109/esime.2006.1644002

[10] Mohammad M Hossain, Yongje Lee, Roksana Akhter, and Dereje Agonafer, Computational Modeling of the Reliability of Stacked Low Density Interconnects Devices, The Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronics Systems, (2006).

DOI: https://doi.org/10.1109/itherm.2006.1645466

[11] Zhaohui Chen, Bin Song, XueFang Wang, Sheng Liu, Thermo-mechanical Reliability Analysis of 3D Stacked-die Packaging with Through Silicon Via, The 11th International Conference on Electronic Packaging Technology & High Density Packaging, (2011).

DOI: https://doi.org/10.1109/icept.2010.5582479

[12] C. I. Chen, S. C. Wu, D. S. Liu, C. Y. Ni and T. D. Yuan, Global-to-Local Modeling and Experiment Investigation of a HFCBGA Package Board-level Solder Joint Reliability, International Microelectronics And Packaging Society, JMEP, Vol. 4, No, 4, 4th Qtr. (2007).

DOI: https://doi.org/10.4071/1551-4897-4.4.186

[13] John H.L. Pang, T.H. Low, B. S. Xion and F. X. Che, Design For Reliability (DFR) Methodology For Electronic Package Assemblies, Electronics Packaging Technology Conference, (2003), pp.470-478.

DOI: https://doi.org/10.1109/eptc.2003.1271567

[14] C. S. Selvanayagam, J. H. Lau, X. Zhang, S. K.W. Seah, K. Vaidyanathan and T. C. Chai, Nonlinear Thermal Stress/ Strain Analyses of Copper Filled TSV (Through Silicon Via) and their Flip-Chip Microbumps, IEEE Electronic Components and Technology Conference, (2008).

DOI: https://doi.org/10.1109/ectc.2008.4550108