Design and Implementation of MIPS Simulator Oriented Memory Hierarchy Research

Ying Biao Yao; Xian Bin Zeng; Guang Pei Zhao

doi:10.4028/www.scientific.net/AMM.236-237.907

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 236-237Design and Implementation of MIPS Simulator...

Design and Implementation of MIPS Simulator Oriented Memory Hierarchy Research

Abstract:

MIPS processor is widely used in embedded system, whose memory hierarchy has such an important effect on the performance and cost that how to design memory hierarchy rapidly is a key problem. To deal with the MIPS memory hierarchy research, we design a MIPS simulator “QtMips”. It is a GUI, Qt-based simulator for MIPS assembly language, which not only collects and analyzes real-time simulation information, but also supports fast memory configuration setting such as hierarchy setting, allocation setting, etc.

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Periodical:

Applied Mechanics and Materials (Volumes 236-237)

Pages:

907-912

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.236-237.907

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Online since:

November 2012

Authors:

Ying Biao Yao, Xian Bin Zeng, Guang Pei Zhao

Keywords:

Memory Hierarchy Design, Memory Simulation, MIPS Simulator

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References

[1] J. Hennessy and D. Patterson, Computer Architecture and Design: A Quantitative Approach, Fourth Edition. San Francisco, CA 94111: Morgan Kaufman Publishers, (2007).

Google Scholar

[2] K. Vollmar and P. Sanderson, MARS: an education-oriented MIPS assembly language simulator, ACM SIGCSE Bulletin, vol. 38 (I), pp.239-243, (2006).

DOI: 10.1145/1124706.1121415

Google Scholar

[3] SR Vegdahl, MIPSPILOT: a compiler-oriented MIPS simulator, Journal of Computing Sciences in Colleges, (2008).

Google Scholar

[4] Kabir M. T, Bari M. T, Haque A. L, ViSiMIPS: Visual simulator of MIPS32 pipelined processor, Computer Science & Education (ICCSE), 2011 6th International Conference, 2011, 788-793.

DOI: 10.1109/iccse.2011.6028756

Google Scholar

[5] Bautista, P. I Cruz, A. Rio, A.C. Reyes, J.A. PROJECT GRAMS: A graphical reconfigurable architecture MIPS simulator. TENCON 2008 - 2008 IEEE Region 10 Conference, 19-21 Nov. 2008: 1 – 5.

DOI: 10.1109/tencon.2008.4766609

Google Scholar

[6] Xiaoguang Ren, Yuhua Tang, Tao Tang, Sen Ye, Huiquan Wang, Jing Zhou, Sim-spm: A SimpleScalar-Based Simulator for Multi-level SPM Memory Hierarchy Architecture , High Performance Computing and Communications (HPCC), 2010 12th IEEE International Conference on , 2010 , Page(s): 17 – 23.

DOI: 10.1109/hpcc.2010.18

Google Scholar

[7] Kumar T.S. Rajesh, Ravikumar C. P, Govindarajan R. Memory Architecture Exploration Framework for Cache Based Embedded SOC. 21st International Conference on VLSI Design, 2008, p.553 – 559.

DOI: 10.1109/vlsi.2008.113

Google Scholar