Confidentiality and Integrity Protection Method Based on One Time Encryption

Article Preview

Abstract:

Abstract. Aiming at current problem of high computing overhead of encryption and authentication, this paper proposes a confidentiality and integrity protection method based on one time encryption. The method packages data block and verification data together, and then encrypts it. The confidentiality is guaranteed by traditional encryption mode and the integrity is guaranteed by decrypted verification data. Analysis and simulation show that the method has less time and space overhead than standard encryption and authentication mode. The method can be applied to other integrity and confidentiality protection schemes, and can meet the performance requirements of the most applications.

You might also be interested in these eBooks

Info:

Periodical:

Pages:

2434-2438

Citation:

Online since:

December 2012

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2013 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

[1] David Lie, Speciftying and Verifying hardware D. Lie, J. Mitchell, C. Thekkath, and M. Horowitz. Specifying and Verifying Hardware for Tamper-Resistant Software. In IEEE Symp. on Security and Privacy, (2003).

DOI: 10.1109/secpri.2003.1199335

Google Scholar

[2] Suh, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas. Efficient memory integrity verification and encryption for secure processors. The 36th International Symposium on Microarchitecture, pp.339-350, (2003).

DOI: 10.1109/micro.2003.1253207

Google Scholar

[3] B. Gassend, G. Suh, D. Clarke, M. Dijk, and S. Devadas. Caches and Hash Trees for Efficient Memory Integrity Verification. In Proc of the 9th International Symposium on High Performance Computer Architecture (HPCA-9), (2003).

DOI: 10.1109/hpca.2003.1183547

Google Scholar

[4] G. E. Suh, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas. Hardware mechanisms for memory integrity checking. In Technical Report MIT-LCS-TR-872, November (2002).

Google Scholar

[5] W. Shi, H. -H. Lee, M. Ghosh, and C. Lu. Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, pages 123–134, September (2004).

DOI: 10.1109/pact.2004.1342547

Google Scholar

[6] Elbaz, R., Champagne, D., Lee, R.B., Torres, L., Sassatelli, G., Guillemin, P. TEC-Tree: A Low Cost and Parallelizable Tree for Efficient Defense against Memory Replay Attacks. In: Cryptographic Hardware and embedded systems (CHES), pages. 289–302, (2007).

DOI: 10.1007/978-3-540-74735-2_20

Google Scholar

[7] Duc, G., Keryell, R.: CryptoPage: An Efficient Secure Architecture with Memory Encryption, Integrity and Information Leakage Protection. In: Jesshope, C., Egan, C. (eds. ) ACSAC2006. LNCS, vol. 4186, p.483–492. Springer, Heidelberg (2006).

DOI: 10.1109/acsac.2006.21

Google Scholar

[8] Waseem Ahmad, Enrico Ng. A Quantitative/Qualitative Study for Optimal Parameter Selection of a Superscalar Processor using SimpleScalar. Computer Sciences Technical Report, (2004).

Google Scholar

[9] A. KleinOsowski, J. Flynn, N. Meares, and D. Lilja. Adapting the spec 2000 benchmark suite for simulation-based computer architecture research. In Proceedings of the International Conference on Computer Design, (2000).

DOI: 10.1007/978-1-4615-1613-2_4

Google Scholar