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Design and Implementation of PAL to LVDS Video Adapter Based on FPGA

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Abstract:

In this paper, based on the FPGA and with a PAL decoder chip, LVDS coding chip and large capacity SRAM, the design and implementation of a PAL system for analog signals to the LVDS conversion of the video signal interface board. First of all, convert the analog signal of PAL to RGB565 digital video signal, and transform the interlaced scan into progressive scan. Then, through the frame rate conversion, resolution expansion etc. algorithm method to handle. Finally, to achieve the interlaced scanning, a resolution of 720×576, 25Hz PAL analog video signal, is converted to a progressive scan, a resolution of 1024×768, 60Hz LVDS video signal transmission. After the measurement, the resolution and frame rate of the video signal conversion interface board are all meet the design requirements. It has been verified the effectiveness of scheme.

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Periodical:

Applied Mechanics and Materials (Volumes 241-244)

Pages:

254-258

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.241-244.254

Citation:

Cite this paper

Online since:

December 2012

Authors:

Ling Fan Wu, Li Jun Yun, Jun Sheng Shi, Kun Wang, Ming Hua Wu

Keywords:

Field-Programmable Gate Array (FPGA), LVDS

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© 2013 Trans Tech Publications Ltd. All Rights Reserved

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