Design of Parallel Operated Counter based on ARM + FPGA

Abstract:

Aiming to solve the problems of long execution count and low frequency of counter which has been largely used in various electronic facilities and PLCs, unlike traditional design that utilize embedded microprocessor software for count operation, this paper proposed a parallel operated counter based on ARM+FPGA. The FPGA counter module consists of count controller, SDRAM dynamic parameter and soft contact state register, the count controller carries out counter operation for timing unit every 1ms, then results from count operation would be saved in counter parameter list of a dual port RAM, when controller commands need to be executed via ARM, the counter will be used as a regular memory unit for W/R operation, thus no executing time would be spared basically, which can well meet the system requirements where large number of controllers are needed. Simultaneously, principles of system composition, count operation control and count operation flow are all introduced followed by which a field test is also carried out for testament of the designed counter system.

• Periodical: Applied Mechanics and Materials (Volumes 241-244)
• Pages: 234-239
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.241-244.234
• Online since: December 2012
• Authors: Ling Yu, Ke Jian Li, Qi Zhong Cai, Wei Zhang
• Keywords: Add/Subtract Counter, ARM, Count Operation Control, Counting Reference Time, Dynamic Parameter, Field-Programmable Gate Array (FPGA), Parallel Operation

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