High Gain and Low Noise Single Balanced Wireless Receiver Front-End Circuit Design

Zhe Yang Huang; Che Cheng Huang; Jung Mao Lin; Chung Chih Hung

doi:10.4028/www.scientific.net/AMM.284-287.2647

Paper Titles

Design of DDS-Like Clock Generator Using Bidirectional Integration
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A Cooperative Relay Scheme Based on Constellation Expansion
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Ergodic Channel Capacity of MIMO Transmission in Spatial Correlated-Fading
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Estimation of OFDM Carrier Frequency Offset Robust to Offset Variation
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High Gain and Low Noise Single Balanced Wireless Receiver Front-End Circuit Design
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Partition-Based Hybrid MIMO Decoding Schemes with Combined Depth- and Breath-First Search
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The Performance Comparison of Sub-1GHz Wireless Personal Area Monitoring Systems
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A Cluster-Based Countermeasure against MAC Layer Attacks in IEEE 802.11 MANETs
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A Study of Bipolar Walsh-Hadamard Coding Method in Optical CDMA Networks
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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 284-287High Gain and Low Noise Single Balanced Wireless...

High Gain and Low Noise Single Balanced Wireless Receiver Front-End Circuit Design

Abstract:

This paper presents a wideband wireless receiver front-end for 3.1-5.0GHz band group-1 (BG-1) WiMedia application. The front-end circuits are designed in 0.18um standard CMOS process. The experimental results show the maximum conversion power gain is 45.5dB; minimum noise figure is 2.9dB. Input return loss is lower than -9.3dB and output return loss is lower than -6.8dB. The maximum LO conversion power is 0dBm. 3dB working frequency is 1.9GHz (3.1GHz-5.0GHz) Total power consumption is 24.3mW including LNA, mixer and all buffers. Total chip area is 1.27mm² including dummy and pads.

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Periodical:

Applied Mechanics and Materials (Volumes 284-287)

Pages:

2647-2651

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.284-287.2647

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Online since:

January 2013

Authors:

Zhe Yang Huang, Che Cheng Huang, Jung Mao Lin, Chung Chih Hung

Keywords:

Front-End, LNA, Mixer, Wideband

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