A Preamplifier-Latch Comparator with Reduced Delay Time for High Accuracy Switched-Capacitor Pipelined ADC

Abstract:

This paper presents a modified preamplifier-latch comparator for minimum latch delay and minimum input referred noise. The ratio of PMOS/NMOS in cross-coupled inverter is verified theoretically and optimized for minimum comparator delay. The cross-coupled load, the cascaded structure and the capacitor neutralization techniques are adopted to reduce the kickback noise and the input referred offset voltage. The comparator circuit is designed in a TSMC 0.35 um/3.3 V 2P4M CMOS process. Simulations show that the delay time of latch is declined by 18 percent after optimization and the maximum transfer delay time is only 384.5 ps. The peak to peak value of kickback noise is only 0.831uV in case of Vin,max=1.25 V, and the Monte Carlo simulation results show that equivalent input referred offset voltage is 4.56mV.

• Periodical: Applied Mechanics and Materials (Volumes 303-306)
• Pages: 1842-1848
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.303-306.1842
• Online since: February 2013
• Authors: Jin Rong Wu, Ying Ju, Zhi Lun Lin, Chu Lian Lin, Xiao Chao Li
• Keywords: Delay Time, Kickback Noise, Low Offset, Preamplifier-Latch Comparator

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