An Improved Phase Comparator for the Fast-Locking All Digital SARDLL

Shi Bin Lu; Tai Long Xu; Chang Yong Zheng; Hao Pan; Jun Ning Chen

doi:10.4028/www.scientific.net/AMM.303-306.1849

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 303-306An Improved Phase Comparator for the Fast-Locking...

An Improved Phase Comparator for the Fast-Locking All Digital SARDLL

Abstract:

An improved phase comparator solution for the fast-locking all digital SARDLL, which can deal with the irregular clock signal and give the signal Comp reflecting the phase relations between input clock and output clock, and the signal LD indicating whether the DLL is locked or not, is presented. The improved solution is justified by the transistor- level post-layout SPICE simulation results.

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Periodical:

Applied Mechanics and Materials (Volumes 303-306)

Pages:

1849-1853

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.303-306.1849

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Online since:

February 2013

Authors:

Shi Bin Lu, Tai Long Xu, Chang Yong Zheng, Hao Pan, Jun Ning Chen

Keywords:

Dead-Lock, Fast-Locking, Phase Comparator, SARDLL

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References

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