A Current Compensation Bitline Sense Amplifier

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Abstract:

A new bitline sense amplifier (SA) for improving performance in the presence of current compensation is analyzed. The proposed scheme utilizes a new leakage current compensation circuit, resulting in a 42.9% reduction in the delay from bitline discharge to the date been read out. Thus, this is very important for higher performance application, especially under advanced technology process.

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590-595

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May 2013

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© 2013 Trans Tech Publications Ltd. All Rights Reserved

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[1] K. Roy, S. Mukhopadhyay and H. Mahmoodi-Meimand, in: Proc. IEEE, Vol. 91 (2003), pp.305-327.

Google Scholar

[2] L. Ya-Chun and H. Shi-Yu, in: IEEE J. Solid-State Circuits, Vol. 43 (2008), pp.1964-1971.

Google Scholar

[3] E. Morifuji, T. Yoshida, M. Kanda, S. Matsuda, S. Yamada and F. Matsuoka, in: IEEE Trans. Electron Devices, Vol. 53 (2006), pp.1427-1432.

DOI: 10.1109/ted.2006.874752

Google Scholar

[4] X. Qi, C. L. Sam, A. Gyure, Y. Luo, M. Shahram, K. Singhal, and D.B. MacMillen, in: IEEE Trans. Circuits and Devices Magazine, Vol. 22 (2006), pp.39-47.

DOI: 10.1109/mcd.2006.272999

Google Scholar

[5] W. Dehaene, S. Cosemans, A. Vignon, F. Catthoor and P. Geens, in: Proc. European Solid State Circuits Conference, 33rd (2007), pp.384-391.

DOI: 10.1109/esscirc.2007.4430324

Google Scholar

[6] K. Agawa, H. Hara, T. Takayanagi and T. Kuroda, in: IEEE J. Solid-State Circuits, Vol. 36 (2001), pp.726-734.

DOI: 10.1109/4.918909

Google Scholar

[7] B. Wicht, S. Paul and D. Schmitt-Landsiedel, in: IEEE J. Solid-State Circuits, Vol. 36(2001), pp.1745-1755.

DOI: 10.1109/4.962297

Google Scholar

[8] M. Sharifkhani, E. Rahiminejad, S.M. Jahinuzzaman and M. Sachdev, in: IEEE Trans. Very Large Scale Integration (VLSI) Systems, Vol. 19 (2011), pp.883-894.

DOI: 10.1109/tvlsi.2009.2039949

Google Scholar

[9] D. Anh-Tuan, K. Zhi-Hui, Y.Kiat-Seng and J.Y.S. Low, in: IEEE Trans. Very Large Scale Integration (VLSI) Systems, Vol. 19(2011), pp.196-204.

Google Scholar

[10] Y. Niki, A. Kawasumi, A. Suzuki, Y. Takeyama, O. Hirabayashi, K. Kushida, F. Tachibana, Y. Fujimura and T. Yabe , in: IEEE J. Solid-State Circuits, Vol. 46 (2011), pp.2545-2551.

DOI: 10.1109/jssc.2011.2164294

Google Scholar

[11] B. Wicht, T. Nirschl and D. Schmitt-Landsiedel, in: IEEE J. Solid-State Circuits, Vol. 39 (2004), pp.1148-1158.

DOI: 10.1109/jssc.2004.829399

Google Scholar