Design of (2, 1, N) Parallel Convolutional Encodes for VLSI

Mao Qiang Duan; Xiao Li Huang

doi:10.4028/www.scientific.net/AMM.321-324.2822

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 321-324Design of (2, 1, N) Parallel Convolutional Encodes...

Design of (2, 1, N) Parallel Convolutional Encodes for VLSI

Abstract:

The characters of more high speed computing and much less low power dissipation are needed to settle for convolutional encodes. In this paper, we present a parallel method for convolutional encodes with SMIC 0.35μm CMOS technology; hardware design and VLSI implementation of this algorithm are also presented. Use this method, parallel circuits structure can be easily designed, which take on excellent characters of more high speed computing and low power dissipation compared with traditional serial shift register structure for convolutional encodes.

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Periodical:

Applied Mechanics and Materials (Volumes 321-324)

Pages:

2822-2827

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.321-324.2822

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Online since:

June 2013

Authors:

Mao Qiang Duan, Xiao Li Huang

Keywords:

Convolutional Encodes, Low Power Dissipation, Parallel Computing

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