Development of High-Speed Transmission Error Dynamic Detection System Based on NIOS-II and USB

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This paper proposes a high-speed transmission error (TE) dynamic detection system based on NIOS-II and USB. The detection system is in the realization of data acquisition on a FPGA chip, and sends the collected data to specialized data transmission circuit by the chip NIOS-II CPU core, the data transmission circuit composed of USB2.0 main control chip and FIFO chip, which can realize the two-direction communication between data acquisition circuit and PC, so as to realize the TE detection of high-speed side.

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883-886

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June 2013

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© 2013 Trans Tech Publications Ltd. All Rights Reserved

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