p.866
p.870
p.875
p.879
p.883
p.889
p.893
p.899
p.903
Development of High-Speed Transmission Error Dynamic Detection System Based on NIOS-II and USB
Abstract:
This paper proposes a high-speed transmission error (TE) dynamic detection system based on NIOS-II and USB. The detection system is in the realization of data acquisition on a FPGA chip, and sends the collected data to specialized data transmission circuit by the chip NIOS-II CPU core, the data transmission circuit composed of USB2.0 main control chip and FIFO chip, which can realize the two-direction communication between data acquisition circuit and PC, so as to realize the TE detection of high-speed side.
Info:
Periodical:
Pages:
883-886
Citation:
Online since:
June 2013
Authors:
Keywords:
Price:
Сopyright:
© 2013 Trans Tech Publications Ltd. All Rights Reserved
Share:
Citation: