32-bit Datapath AES IP Core Based on FPGA

Hong Wei Tang

doi:10.4028/www.scientific.net/AMM.336-338.1848

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32-bit Datapath AES IP Core Based on FPGA
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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 336-33832-bit Datapath AES IP Core Based on FPGA

32-bit Datapath AES IP Core Based on FPGA

Abstract:

This paper presents an architecture for 32-bit datapath Advanced Encryption Standard(AES) IP core based on FPGA. It uses finite state machine, and supports encryption, decryption and key expansion. The round-key is calculated before the beginning of encryption and decryption. It consumes less hardware resources. It is implemented on Cyclone II FPGA EP2C35F672C6, which consumes less than 55% logic elements of the resources. The IP core can operate at a maximum clock frequency of 100 MHz. Compared with 128-bit datapath AES, it can interface with CPU easily.