Design and Implementation of CABAC Parallelization on Multicore DSP

Hong Xu Jiang; Wei Zhao; Xiao Hong Zhang; Jin Yuan Lu

doi:10.4028/www.scientific.net/AMM.340.685

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 340Design and Implementation of CABAC Parallelization...

Design and Implementation of CABAC Parallelization on Multicore DSP

Abstract:

This work mainly focus on the design and implementation of context-based adaptive binary arithmetic coding (CABAC) parallelization on multicourse digital signal processor (DSP) platform. Syntax elements partitioning based on load balancing is proposed to achieve data parallelization of CABAC. On the multicourse DSP, a task-dispatch structure is proposed. Inter-core communication is achieved by combination of shared memory and interrupt. And inter-core synchronization is achieved by combination of shared variable and hardware semaphore. The above structure makes the overall system clearer and program control easier. A speedup of 2.77 is obtained.

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Periodical:

Applied Mechanics and Materials (Volume 340)

Pages:

685-690

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.340.685

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Online since:

July 2013

Authors:

Hong Xu Jiang, Wei Zhao, Xiao Hong Zhang, Jin Yuan Lu

Keywords:

CABAC, Digital Signal Processor (DSP), Multicourse Parallelization

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