A Novel Fault Orientation Technique of FPGA Configurable Logic Blocks Based on Improved Shift Register

Abstract:

With the development of digital integrate circuit system which is based on Field Programmable Gate Arrays (FPGA), the request on FPGA test technique is becoming higher and higher. The Boundary Scan Technique and Built-In Self-Test (BIST) technique appear in succession, however, these techniques dont implement Configurable Logic Block (CLB) fault diagnose and fault orientation. Arrays-based technique was advanced, which also have some problems about masking of faults and too many reconfiguration times. According to these problems, A Novel Shift Register-based technique for Fault Orientation of FPGA Configurable Logic Blocks was advanced. The paper analyses the design theory about core circuit configure, and has important significance impact on Fault Orientation of FPGA Configurable Logic Blocks.

• Periodical: Applied Mechanics and Materials (Volumes 347-350)
• Pages: 1602-1606
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.347-350.1602
• Online since: August 2013
• Authors: Jun Bin Zhang, Jin Yan Cai, Dan Yang Li
• Keywords: Evolvable Arithmetic, Fault Diagnose, Field-Programmable Gate Array (FPGA), Shift Register, Test Vectors

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