Time Delay Model for SRAM Compiler

Qiang Song; Chun Yu Peng; Hong Gang Zhou; Shou Biao Tan

doi:10.4028/www.scientific.net/AMM.373-375.1561

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 373-375Time Delay Model for SRAM Compiler

Time Delay Model for SRAM Compiler

Abstract:

In this paper, we introduced an effective time delay model for SRAM compiler, which represents an important performance of SRAM. Our method divide the delay time into several periods, including decoder delay, word line delay, bit line delay and SA delay. The theory is useful in predicting the delay time when the SRAM size is changed. Simulations by Hsim in 65nm CMOS process proves a high accuracy.

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Periodical:

Applied Mechanics and Materials (Volumes 373-375)

Pages:

1561-1566

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.373-375.1561

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Online since:

August 2013

Authors:

Qiang Song, Chun Yu Peng, Hong Gang Zhou, Shou Biao Tan

Keywords:

Bit Line, Decoder, Model, TCQ, Time Delay, Word Line

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References

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