Signal Detection Technology for Low Voltage Arc Fault Circuit Interrupter Using FPGA

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This paper is studying the low voltage arc fault circuit interrupters (AFCI) based on FPGA Signal detection. The arc fault generator is designed to generate artificial low voltage series arc faults. The AFCI signal detection circuits are tested by using the measured voltage and current waveforms from the testing circuits. It is expect to develop high performance signal detection circuits and the key component using in AFCI. Finally, the experimental data with serial arc faults are used to test the detecting methods and compare with the commercial devices. The purposed detecting methods can effectively detect the occurring of series arc faults, and the probability of malfunction is low.

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451-454

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August 2013

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© 2013 Trans Tech Publications Ltd. All Rights Reserved

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[1] UL Standard 1699, Arc-Fault circuit interrupters, Illinois, U.S.A., (2008).

Google Scholar

[2] C. Kang, The operation characteristics of circuit design in arc fault current interruption, proceedings of the 6th WSEAS International Conference on Heat and Mass Transfer (HMT'09). 1 (2009) 85-88.

Google Scholar

[3] G. Gregory, K. Wong, and R. Dvorak, More about arc-fault circuit interrupters, IEEE Transactions on Industry Applications. 40 (2004) 1006-1011.

DOI: 10.1109/tia.2004.831287

Google Scholar

[4] P. Muller, S. Tenbohlen, R. Maier, and M. Anheuser, Characteristics of series and parallel low current arc faults in the time and frequency domain, Proceedings of the IEEE Holm Conference on Electrical Contacts. 1 (2010) 1-7.

DOI: 10.1109/holm.2010.5619539

Google Scholar

[5] I. Kim Park, S. Choi, and G. Kil, Detection algorithm of aeries arc for electrical fire prediction, Proceedings of the International Conference on Condition Monitoring and Diagnosis. 1 (2008) 716 - 719.

DOI: 10.1109/cmd.2008.4580385

Google Scholar

[6] J. Anderson and F. Najm, Active leakage power optimization for FPGAs, IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems. 25 (2006) 423-437.

DOI: 10.1109/tcad.2005.853692

Google Scholar

[7] F. Li, Y. Lin, L. He, D. Chen and J. Cong, Power modeling and characteristics of field programmable gate arrays, IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems. 24 (2005) 1712-1724.

DOI: 10.1109/tcad.2005.852293

Google Scholar