[1]
Simevski A, Kraemer R, Krstic M. Platform for automated HW/SW co-verification, testing and simulation of microprocessors [C]. Test Workshop (LATW), 2012 13th Latin American: IEEE, 2012, 1-5.
DOI: 10.1109/latw.2012.6261242
Google Scholar
[2]
B. Turumell,M. Sharma. Assertion-based verification of a 32 thread sparctm cmt micrprocessor. In Design Automation Conference, 2008. DAC2008, 45thACM/IEEE, pages 256-261, june (2008).
DOI: 10.1145/1391469.1391535
Google Scholar
[3]
Janick Bergeron Eduard Cerny Alan Huter Andrew Nightngale. Methodology Manual for SystemVerilog [M], 2007: 86-171.
Google Scholar
[4]
Mark Glasser. Open Verification Methodology Cookbook[M], (2009).
Google Scholar
[5]
Banerjee S, Gupta T. Design aware scheduling of dynamic testbench controlled design element accesses in FPGA-based HW/SW co-simulation systems for fast functional verification [C]. Quality Electronic Design (ASQED), 2010 2nd Asia Symposium on: IEEE, 2010, 175-181.
DOI: 10.1109/asqed.2010.5548239
Google Scholar
[6]
Ruan A, Wang Y, Shi K, Zhu Z, Wu Q, Han X, Liao Y. SOC HW/SW co-verification technology for application of FPGA test and diagnosis [C]. Computational Problem-Solving (ICCP), 2011 International Conference on: IEEE, 2011, 1-6.
DOI: 10.1109/iccps.2011.6092258
Google Scholar
[7]
Huang X, Liu LT, Li YJ, Liu LC, Huang XZ. FPGA verification methodology for SiSoC based SoC design [C]. Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of: IEEE, 2011, 1-2.
DOI: 10.1109/edssc.2011.6117612
Google Scholar
[8]
Lulu Feng, Zibin Dai, Wei Li, Jianlei Cheng. Design and application of reusable SoC verification platform. ASIC(ASICON), 2011 IEEE 9th International Conference, pages 957-960, oct, (2011).
DOI: 10.1109/asicon.2011.6157365
Google Scholar
[9]
CUI Guang-Zuo, CHENG Xu, TONG Dong, and LIU Qiang. SYSTEM-LEVEL SIMULATION, EMULATION AND DEBUGGING TECHNOLOGY FOR PROCESSOR—NEW METHODOLOGY BASED ON HARDWARE/SOFTWARE CODESIGN[J]. JOURNAL OF COMPUTER RESEARCH & DEVELOPMENT, 2001, Vol. 38, No. 3. 361-367.
Google Scholar
[10]
Chris Spear. SystemVerilog for Verification [M], 2009: 65-102.
Google Scholar