Design of DVB-S2 LDPC Coder and Decoder Implemented in FPGA

Jun Wen Sun; Shuang Shuang Yin

doi:10.4028/www.scientific.net/AMM.380-384.3093

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 380-384Design of DVB-S2 LDPC Coder and Decoder...

Design of DVB-S2 LDPC Coder and Decoder Implemented in FPGA

Abstract:

Full parallel architecture for DVB-S2 LDPC was implemented on the platform of FPGA, in this process, the pipeline technology was introduced, and the method of FIFO and multiple RAM group used at the same time was also used, the problem of storing the parity check matrix was effectively overcomed, and the coding rate reaches 125Mbps. In order to solve the problem of high consumption of resources, the design of decoder adopted serial architecture, the decoding delay was greatly reduced by clever design of interleaver structure, and the decoding throughput reaches 125Mbps, moreover utilization of registers and logic elements is less than 1%.

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Periodical:

Applied Mechanics and Materials (Volumes 380-384)

Pages:

3093-3097

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.380-384.3093

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Online since:

August 2013

Authors:

Jun Wen Sun, Shuang Shuang Yin

Keywords:

Coder/Decoder, Field-Programmable Gate Array (FPGA), Low-Density Parity-Check (LDPC) Codes, Second Generation Satellite Digital Video Broadcasting Standard (DVB-S2)

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References

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