FPGA Implementation of High-Speed Memory Efficient Quasi-Cyclic LDPC Decoder

Jian Bing Han; Chen He; Ran Zhen

doi:10.4028/www.scientific.net/AMM.380-384.3328

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 380-384FPGA Implementation of High-Speed Memory Efficient...

FPGA Implementation of High-Speed Memory Efficient Quasi-Cyclic LDPC Decoder

Abstract:

This paper introduces a new kind of decoder structure for FPGA implementation of high-speed memory efficient quasi-cyclic LDPC (QC-LDPC) decoder. The code structure, algorithm and hardware structure all adopt optimization design. The decoder adopts modified Turbo decoding algorithm and achieves a decoding throughput of 223 Mbps and frame size of 3,200 bits. The Xilinx Virtex-4 chip used by the decoder only takes up 71 KB memory and makes it exceeds other decoders in aspects of throughput and memory for FPGA implementation.

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Periodical:

Applied Mechanics and Materials (Volumes 380-384)

Pages:

3328-3331

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.380-384.3328

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Online since:

August 2013

Authors:

Jian Bing Han, Chen He, Ran Zhen

Keywords:

Decoder, Field-Programmable Gate Array (FPGA), Memory Efficient, Quasi-Cyclic LDPC

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