High Performance FPGA Implementation of Floating Point Addition

Hui Jing Yang; Fan Yu; Dan Dan Han

doi:10.4028/www.scientific.net/AMM.380-384.3316

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High Performance FPGA Implementation of Floating Point Addition
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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 380-384High Performance FPGA Implementation of Floating...

High Performance FPGA Implementation of Floating Point Addition

Abstract:

Addition is the most frequent floating point operation in modern microprocessors. The design of floating point addition is relatively complex than other flotation point arithmetic operations. Due to its complex shift-add-shift-round data flow, floating point addition can have a long latency. This paper has shown an efficient implementation of addition module on a reconfigurable platform cyclone IV EP4CE15, which is both area as well as performance optimal. The proposed design has optimized the individual complex components of adder module (like dynamic shifter, leading one detector (LOD), priority encoder), to achieve the better overall implementation. Comparison with the best reported.

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Periodical:

Applied Mechanics and Materials (Volumes 380-384)

Pages:

3316-3319

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.380-384.3316

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Online since:

August 2013

Authors:

Hui Jing Yang, Fan Yu, Dan Dan Han

Keywords:

Field-Programmable Gate Array (FPGA), Floating Point, Leading One Prediction, Redundant Format, Two Path Arithmetic

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