Design of a Low-Power Rail-to-Rail CMOS Operational Amplifier

Yang Guang; Bin Yu; Huang Hai

doi:10.4028/www.scientific.net/AMM.380-384.3304

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 380-384Design of a Low-Power Rail-to-Rail CMOS...

Design of a Low-Power Rail-to-Rail CMOS Operational Amplifier

Abstract:

In this paper, an operational amplifier with low-power consumption has been designed. Using the complementary differential pair for the input stage and the class AB structure for the output stage, the common-mode input range and output swing of the proposed circuit could achieved rail-to-rail. Based on TSMC 0.18μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that the proposed op-amp has more than 100dB open loop gain, meanwhile the static power consumption is less than 300μw. The circuit's phase margin is 68 degrees, CMRR is 135dB and power supply rejection ratio is 63dB.

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Periodical:

Applied Mechanics and Materials (Volumes 380-384)

Pages:

3304-3307

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.380-384.3304

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Online since:

August 2013

Authors:

Yang Guang, Bin Yu, Huang Hai

Keywords:

Amplifier, Low-Power, Rail-To-Rail

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References

[1] Ahmadi M M, An Adaptive Biased Single_stage CMOS Operational Amplifier with a Novel Rail-to-Rail Constant-gm Input stage, Analog Integrated Circuit and Signal Processing, 2005, 45: 71-78.

DOI: 10.1007/s10470-005-3425-9

Google Scholar

[2] Loikkanen M, Kostamovaara J. Low Voltage CMOS Power Amplifier with Rail-to-Rail Input and Output, [J]. Analog Integral Circuits Process, 2006, 46-183.

DOI: 10.1007/s10470-006-1478-z

Google Scholar

[3] Stockstand T, Yoshizawa H. A 0. 9-V 0. 5 A rail-to-rail CMOS operational amplifier, IEEE J Solid State Circuits 2002; 37: 286-292.

DOI: 10.1109/4.987079

Google Scholar

[4] P.E. Allen and D.R. Holberg, CMOS Analog Circuit design-2nd Ed,., Oxford University Press, (2002).

Google Scholar

[5] Behzad Razavi Design of analog CMOS integrated circuits,. McGraw–Hill; (2001).

Google Scholar