FPGA Implementation of a Novel Multi-Rate QC-LDPC Encoder for DTMB Standard

Fei Wang; Peng Zhang; Chang Yin Liu

doi:10.4028/www.scientific.net/AMM.397-400.2024

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 397-400FPGA Implementation of a Novel Multi-Rate QC-LDPC...

FPGA Implementation of a Novel Multi-Rate QC-LDPC Encoder for DTMB Standard

Abstract:

A serial-input serial-output encoder based on pipelined type I rotate-left-accumulator (RLA) circuit is presented for multi-rate Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes of Digital Terrestrial Multimedia Broadcasting (DTMB) standard. This encoding scheme can reduce the power consumption and save memory resource. FPGA implementation and simulation results show that the design meets the requirement of DTMB standard and simplifies the structure of the memory.

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Periodical:

Applied Mechanics and Materials (Volumes 397-400)

Pages:

2024-2027

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.397-400.2024

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Online since:

September 2013

Authors:

Fei Wang, Peng Zhang, Chang Yin Liu

Keywords:

Encoder, Field-Programmable Gate Array (FPGA), Qc-LDPC, RLA

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