Using VMM and Verification IP to Verify an AHB-Based Design

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This paper describes the use of VMM, Verification IP, and several of the new VMM Applications to quickly develop a verification environment for an AHB-Based system. VIP such as Synopsys DesignWare AHB Master and Monitor transactors enabled generation of valid transaction and ensured AHB protocol compliance. VMM sub-environment were used to encapsulate these components and simplify their reuse in higher level test environment.

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688-691

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September 2013

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© 2013 Trans Tech Publications Ltd. All Rights Reserved

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[1] Janick Bergeron, Eduard Cerny, Alan Hunter and Andrew Nightingale. Verification Methodology Manual for SystemVerilog. 2005, Springer.

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[2] Chris Spear. SystemVerilog for Verification, A Guide to Learning the Testbench Language Features. 2008, Springer.

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[3] DesignWare Serial I/O Verification IP VMM User Manual. 2011, Synopsys.

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