Research and Design of Superscalar Pipeline Processor Based on CPLD Technology

Chang Qin Yan; Yan Yan Yu; Qian Huang; Jun Yang

doi:10.4028/www.scientific.net/AMM.427-429.2822

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 427-429Research and Design of Superscalar Pipeline...

Research and Design of Superscalar Pipeline Processor Based on CPLD Technology

Abstract:

Superscalar pipelining is to improve instruction-level parallelism and advanced technology, and is widely used in the computer's central processor and graphic accelerator. In this paper, we made use of advantage of CPLD devicesinherent flexibility, usability, predictability and so on, to achieve superscalar pipelining, designed and constructed a processor model superscalar pipeline machine based on RISC instruction set. Using EDA technology with top-down design methods, and gave the processor model hardware verification and performance test results, and had explored the use of EDA technology processor design ideas and methods.

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Periodical:

Applied Mechanics and Materials (Volumes 427-429)

Pages:

2822-2825

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.427-429.2822

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Online since:

September 2013

Authors:

Chang Qin Yan*, Yan Yan Yu, Qian Huang, Jun Yang

Keywords:

CPLD, EDA, RISC, Superscalar Pipeline

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* - Corresponding Author

References

[1] Xiaofei Wu. Architecture design of Superscalar embedded TURB052 microcontroller. Application of Electronic Technique (2009) p.62.

Google Scholar

[2] Kun Yang, Deyuan Gao and Xiaoping Huang. Design of the Instrucion Issue algorithm for RISC Superscalar microprocessor . Microelectronics & Computer (2010) p.8.

Google Scholar

[3] Jie Chen, Lihong Jiang and Hongming Cai. A Mathematical Planning Model Founded on Superscalar Pipelining Scheduling. COMPUTER SIMULATION(2009) p.244.

Google Scholar

[4] Wenbo Liu and Xuezeng Pan. Design of Hardware Pipelining Processor. COMPUTER ENGINEERING (2010) p.278.

Google Scholar

[5] Zhenghong Deng. Research and Application on Superscalar Microprocessors. MICROELECTRONICS & COMPUTER (2006) p.21.

Google Scholar

[6] EVERS. M and YEH.T. Y. Understanding branches and designing branch predictors for high-performance microprocessors. Proceedings of the IEEE (2001) p.1109.

DOI: 10.1109/5.964441

Google Scholar

[7] Haimin Chen, Zheng Li and Rui Jiao. Design and realization of branch prediction for embedded microprocessor. JOURNAL OF COMPUTER APPLICATIONS (2011) p.26.

Google Scholar

[8] Jinhua Yang, Songhua Yang and Kun Zhang. An On-chip Debug Mode for Embedded Microprocessors. CONTROL & AUTOMATION (2005) p.18.

Google Scholar

[9] He Zhang. Study of reorder buffer in superscalar processors. INFORMATIONIZATION (2009) p.16.

Google Scholar

[10] Gang Zhang. Discussion of Teaching Points and Methods for Multiple Issue Strategy of Superscalar Pipeline. COMPUTER EDUCATION (2010) p.36.

Google Scholar