Implementation of ESD Protection for Output Driver ICs with SCR Circuits Techniques

Abstract:

In this paper, an output driver which drove a large current in DC brushless fan ICs was taken for the HBM ESD stress. The protection circuits of this IC were also designed to improve ESD robustness by various layout parameters and structures. From the ESD testing results, it was found that the positive Pad-to-VSS (PS) zapping mode was weakest for the output driver of DC brushless fan ICs during ESD stress. Eventually, protection circuits with a complementary low-voltage-triggered SCR (LVTSCR) were used to protect the whole-chip ESD stress. After a systematic improvement, an SCR structure of adding protection circuits can effectively protect the whole-chip ESD reliability, as compared with the original DUT; the ESD failure threshold (V_ESD) of PS mode is increased 314% in a best structure when an LVTSCR with the drain-tap S space is 4μm.

• Periodical: Applied Mechanics and Materials (Volume 464)
• Pages: 139-144
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.464.139
• Online since: November 2013
• Authors: Shen Li Chen*, Der Ann Fran
• Keywords: Drain-Contact to Poly-Gate Edge (DCG), Electrostatic Discharge (ESD), ESD Failure Threshold (V_ESD), Human-Body Model (HBM), Latch-Up (LU), Low-Voltage-Triggered SCR (LVTSCR), Positive Pad-To-VSS (PS) Mode

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