Design of Image Data Cache System Based on Nios II/s Soft-Core Processor

Abstract:

A design of image data cache system based on Nios II/(s) high performance soft-core processor is presented in our study. The FPGA, the image acquisition chip, the Nios II/(s) high performance soft-core processor, were selected together with the memory constitute the designed system to realize the prospective function. The principle of each specific function module in our study was discussed and analyzed, and the design of software and hardware were more perfectly. We found that the designed system presented an excellent generality, feasibility, reliability during the test course, which can be used in integrated sensor networks for environment and tracffic monitoring in urban areas.

• Periodical: Applied Mechanics and Materials (Volumes 513-517)
• Pages: 1499-1502
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.513-517.1499
• Online since: February 2014
• Authors: Ying Jiang Li*, Rui Li, Li Yan
• Keywords: ADV7180, CY7C68013, IIC, Image Acquisition, Nios II/s

References

[1] L. Y. Lin, L. Wu. Single chip computer IIC bus realization based on the software simulation of 51 [J]. Electronic technology, 2004 (05): 13-15.

[2] C. F. Zhu, T. J. Xiao. Image acquisition system designing based on the FPGA video [J]. Computer engineering and design, 2008, 9 (17): 4404-4406.

[3] G. Z. Chen, T. Liu, Y. Z. Li. Image acquisition and memory design based on FPGA [J]. Mechanical engineering and automation, 2007, 8 (4): 44-45.

[4] G. B. Zhang, L. J. Meng, B. G. Li. CCD camera high speed data storage system in seamless cache technology [J], Hydropower energy science and technology, 2010, 2 (2): 70-71.

[5] Erenyi, I et. al, Fpga-Based Automated Datapath Design, EUROMICRO 97, 664: 1-4, (1997).