A Novel Bit-Flipping LDPC Decoder for Solid-State Data Storage

Abstract:

This paper concerns the design of high-speed and low-cost LDPC code bit-flipping decoder. Due to its inferior error correction strength, bit-flipping decoding received very little attention compared with message-passing decoding. Nevertheless, emerging flash-based solid-state data storage systems inherently favor a hybrid bit-flipping/message-passing decoding strategy, due to the significant dynamics and variation of NAND flash memory raw storage reliability. Therefore, for the first time highly efficient silicon implementation of bit-flipping decoder becomes a practically relevant topic. To address the drawbacks caused by the global search operation in conventional bit-flipping decoding, this paper presents a novel bit-flipping decoder design. Decoding simulations and ASIC design show that the proposed design solution can achieve upto 80% higher decoding throughput and meanwhile consume upto 50% less silicon cost, while maintaining almost the same decoding error correction strength.

• Periodical: Applied Mechanics and Materials (Volumes 513-517)
• Pages: 2094-2098
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.513-517.2094
• Online since: February 2014
• Authors: Wen Zhe Zhao*, Kai Zhao, Qiu Bo Chen, Min Jie Lv, Zuo Xun Hou
• Keywords: Low-Density Parity-Check Codes, Solid-State Data Storage, Very-Large-Scale Integration

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