A Power Supply On-Chip with Low Power Dissipation for Low Power Digital Integrated Circuit Applications

Hai Peng Zhang; Shao Dan Yang; Ya Dong Yin; De Jun Wang

doi:10.4028/www.scientific.net/AMM.513-517.3844

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 513-517A Power Supply On-Chip with Low Power Dissipation...

A Power Supply On-Chip with Low Power Dissipation for Low Power Digital Integrated Circuit Applications

Abstract:

An implementation method of a power supply on-chip (PSOC) was presented for low power digital integrated circuit (IC) applications in this paper. The PSOC consists of a main power supply and a backup low power dissipation power supply, which is featured of micro-standby power consumption and fast switching. The PSOC was designed according to the design rules of SMIC 0.18μm CMOS process and validated both through simulation and silicon verification. The active area is about 0.035mm² in fact. Post-layout simulation results indicate that output voltage of the PSOC is regulable in the range of 1.52~2.5V as input voltage is in the range of 2.0~3.6V, in which output of the main power supply is regulable in the range of 1.75~ 1.84V. The maximum quiescent current of main power supply is 16.23μA, while the maximum quiescent current of standby power is only 0.552μA. Experimental results indicate that the PSOC is capable of providing energy for the system digital IC implementation. Its power switching time is less than 148μs at the load capacitance of C_L=56nF.

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Periodical:

Applied Mechanics and Materials (Volumes 513-517)

Pages:

3844-3849

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.513-517.3844

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Online since:

February 2014

Authors:

Hai Peng Zhang*, Shao Dan Yang, Ya Dong Yin, De Jun Wang

Keywords:

Digital ICs, Low-Power Dissipation, Power Supply On-Chip (PSOC), Standby Power Supply

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