Large Capacity Cache Design Based on Emerging Non-Volatile Memory

Abstract:

A triple-level-cell (TLC) STT-RAM architecture was proposed basing on parallel MLC MTJ and serial MLC MTJ. A TLC STT-RAM cell can store three bit which will offer higher capacity density compared with SLC STT-RAM. The write process is also analyzed that it contains three types of basic states transitions. Through mapping soft, medium and hard domains to three individual cache lines, the access to soft lines can perform as accessing SLC STT-RAM-based cache. The amount of three-step operations is also much reduced. .

• Periodical: Applied Mechanics and Materials (Volumes 513-517)
• Pages: 918-921
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.513-517.918
• Online since: February 2014
• Authors: Kai Bu*, Hai Jun Liu, Hui Xu, Zhao Lin Sun
• Keywords: Cache, MLC, MTJ, STT-RAM, TLC

References

[1] Y. Chen, X. Wang, W. Zhu, H. Li, Z. Sun, G. Sun, and Y. Xie. Access Scheme of Multi-Level Cell Spin-Transfer Torque Random Access Memory and Its Optimization,. In 53rd IEEE International Midwest Symposium on Circuits and Systems, pages 1109 –1112, Aug. (2010).

DOI: 10.1109/mwscas.2010.5548848

[2] Y. Chen, W. -F. Wong, H. Li, and C. -K. Koh. Processor Caches Built Using Multi-Level Spin-Transfer Torque RAM Cells,. In International Symposium on Low Power Electronics and Design 2011, pages 73 –78, Aug. (2011).

DOI: 10.1109/islped.2011.5993610

[3] Sun, Z.; Bi, X.; Li, H.; Wong, W. -F.; Zhu, X., STT-RAM Cache Hierarchy With Multiretention MTJ Designs, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol. PP, no. 99, p.1, 1, 0.

DOI: 10.1109/tvlsi.2013.2267754

[4] Yaojun Zhang; Lu Zhang; Wujie Wen; Guangyu Sun; Yiran Chen, Multi-level cell STT-RAM: Is it realistic or just a dream?, Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on , vol., no., p.526, 532, 5-8 Nov. (2012).

DOI: 10.1145/2429384.2429498

[5] X. Lou, Z. Gao, D. V. Dimitrov, and M. X. Tang, Demonstration of multilevel cell spin transfer switching in MgO magnetic tunnel junctions, Applied Physics Letter, vol. 93, p.242502, (2008).

DOI: 10.1063/1.3049617

[6] T. Ishigaki, T. Kawahara, R. Takemura, K. Ono, K. Ito, H. Matsuoka, and H. Ohno. A Multi-level-cell Spin-transfer Torque Memory with Seriesstacked Magnetotunnel Junctions,. In Symposium on VLSI Technology, pages 47 –48, Jun. (2010).

DOI: 10.1109/vlsit.2010.5556126

[7] Wei Xu; Hongbin Sun; Xiaobin Wang; Yiran Chen; Tong Zhang, Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM), Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol. 19, no. 3, p.483, 493, March.

DOI: 10.1109/tvlsi.2009.2035509

[8] Guangyu Sun; Xiangyu Dong; Yuan Xie; Jian Li; Yiran Chen, A novel architecture of the 3D stacked MRAM L2 cache for CMPs, High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on , vol., no., p.239, 249, 14-18 Feb. (2009).

DOI: 10.1109/hpca.2009.4798259