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Realization and Simulation of High Speed Flexible Transmission System between FPGA Chips Based on SRIO

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Abstract:

This paper issued a new scheme that passing the configuration information of SRIO to FPGA through EMIF interface, so that two FPGAs can transfer data to each other dynamically for different ways of data interaction. In a word, this paper provides a flexible high-speed transmission scheme for the TD-LTE RF conformance test instrument development.

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Info:

Periodical:

Applied Mechanics and Materials (Volumes 543-547)

Pages:

1967-1971

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.543-547.1967

Citation:

Cite this paper

Online since:

March 2014

Authors:

Xiao Wen Li*, Xiao Zhong Liu, Ming Li, Wei Nan Wu

Keywords:

EMIF Interface, FPGA, SRIO, Td-LTE Rf Conformance Test Instrument

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Сopyright:

© 2014 Trans Tech Publications Ltd. All Rights Reserved

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References

[1] Xilinx FPGA LogiCORE™ IP Serial RapidIO v5. 6 Getting Srarted Guide, (2011).

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[2] Xilinx FPGA LogiCORE™ IP Serial RapidIO v5. 6 User's Guide, (2011).

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[3] TMS320C645x DSP External Memory Interface (EMIF) User's Guide, (2008).

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[4] TEXAS INSTRUMENTS TMS320C6455 Fixed -Point Digital Signal Processor, 159-169.

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[5] Xiayuwen. Verilog Digital system design, version 2. Beijing: Beijing University of Aeronautics and Astronautics Press, (2008).

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[6] Yujian, the SRIO Interconnect design between FPGA and DSP, Optic Technology Application, 2012, 33(6), 902-905.

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