A Design for Clock Synchronization Using CPPLL

Xiao Wang; Zhi Bin Zeng

doi:10.4028/www.scientific.net/AMM.543-547.558

Paper Titles

Power Distributing Network Client Query Methods Based on Tree Structure Database
p.537

Design in Laboratory Equipment for Power Generate and Supply System of New Type Self-Propelled Gun
p.541

Performance Simulation of an EM-Based Iterative Receiver for Underwater Acoustic OFDM System
p.547

The Design and Implementation of RTOS Based on YL-236 Single Chip Microcomputer Training Device
p.554

A Design for Clock Synchronization Using CPPLL
p.558

Design and Realization of a Full Digitalization GMSK Modem on FPGA
p.562

The Design and Implementation of a High-Speed and Large-Capacity NAND Flash Storage System
p.568

Design of Integrated Circuit of Electronic Musical Instruments and Leakage Protection Device
p.572

Research on Aerodynamic Characteristics of Thermal Power Based on Improved GAMBIT Simulation
p.576

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 543-547A Design for Clock Synchronization Using CPPLL

A Design for Clock Synchronization Using CPPLL

Abstract:

High performance clock synchronization system is essential in communication transmission, which is based on the principle of phase locked loop synchronization that tracking a high accuracy, high stability reference clock source usinh low-pass filter to turn the value into voltage and to control VCO or VXCO and makes the output frequency and the input frequency to maintain strict synchronization.

You might also be interested in these eBooks

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volumes 543-547)

Pages:

558-561

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.543-547.558

Citation:

Cite this paper

Online since:

March 2014

Authors:

Xiao Wang*, Zhi Bin Zeng

Keywords:

Clock Synchronization, CPPLL, Frequency Lock, Loop Filter

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

* - Corresponding Author

References

[1] Roland E. Best. Phase-Locked Loops: Design, Simulation, and Applications. U.S. A: McGraw-Hill, 2003. 3-21.

Google Scholar

[2] Neda Nouri and Shahriar Mirabbasi. A 900MHz-2GHz Low-Swing Low-Power 0. 18µm CMOS PLL. Canadian Conference on Electrical and Computer Engineering, 2005, 5: 1558-1561.

DOI: 10.1109/ccece.2005.1557278

Google Scholar

[3] Patrik Larsson. A 2-1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability. IEEE Journal of Solid-State Circuits, 1999, 34(12): 1951-(1960).

DOI: 10.1109/4.808920

Google Scholar

[4] Patrik Lasson. A 2-1600MHz 1. 2-2. 5V CMOS Clock-Recovery PLL with Feedback Phase-Selection and Averaging Phase-Interpolation for Jitter Reduction. IEEEInternational Solid-State Circuits Conference, 1999, 2: 356-357.

DOI: 10.1109/isscc.1999.759294

Google Scholar

[5] Razavi Behzad. Design of Analog CMOS Integrated Circuits. U.S. A: McGraw-Hill, 2001: 532-576.

Google Scholar

[6] Julien Roche, Wenceslas Rahadjandrabe, Lahkadar Zad, et al. A PLL with LoopBandwith Enhancement for Low-Noise and Fast-Settling Clock Recovery. IEEE International Conference on Electronics, Circuits and Systems, 2008, 8: 802-805.

DOI: 10.1109/icecs.2008.4674975

Google Scholar

[7] Biju Viswanathan, Vijay Viswam, Kulanthaivelu R, et al. 4 GHz 130nm Low Voltage PLL Based on Self Biased Technique. 23th International Conference on VLSI Design, 2010, 1: 330-334.

DOI: 10.1109/vlsi.design.2010.21

Google Scholar