The Design and Implementation of a High-Speed and Large-Capacity NAND Flash Storage System

Abstract:

Now, the quality of higher speed and larger capacity are required to the real-time storage system. This paper designs a high-speed and large-capacity storage system which uses FPGA as the master of SOPC system controlling NAND Flash chips. This system puts forward an advanced storage structure which has several NAND Flashes with multi-buses, forming a parallel pipeline design. By using the key technologies of bad block management and the ECC algorithm, which greatly avoids the influence of the invalid block to the storage system and reduces the probability of error data as well. It can not only improve the storage bandwidth and capacity substantially, but also ensure the reliability of the storage system effectively. As a result, the storage system achieves the capacity of 1.5TB and the bandwidth of 1280MBps. Also, this system uses high-speed exchange interface to link to the external network, which achieve the real-time transmission and control of data, and make the storage system standard, universal, and scalable.

• Periodical: Applied Mechanics and Materials (Volumes 543-547)
• Pages: 568-571
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.543-547.568
• Online since: March 2014
• Authors: Qing Li, Shan Qing Hu*, Yang Feng, Teng Long
• Keywords: ECC, FPGA, High-Speed, Large Capacity, NAND Flash

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