A High-Speed 64b/66b Decoder Used in SerDes

Abstract:

A high-speed 64b/66b decoder for SerDes system was designed in TSMC 0.18-μm CMOS Technology. The chip is composed of Block Sync, Descrambler, Decode Process and Receive Control. To make the system can be work in high speed, we use a lot of technology such as pipeline strategy, optimization of complicated logics and parallel descrambler.

• Periodical: Applied Mechanics and Materials (Volumes 556-562)
• Pages: 1549-1552
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.556-562.1549
• Online since: May 2014
• Authors: Bin Wang*, Qing Sheng Hu
• Keywords: 64b/66b Decoder, Block Sync, Parallel Descramble

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