A Design of CPPLL for CMMB Broadcasting System

Xiao Wang; Zhi Bin Zeng

doi:10.4028/www.scientific.net/AMM.556-562.1597

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 556-562A Design of CPPLL for CMMB Broadcasting System

A Design of CPPLL for CMMB Broadcasting System

Abstract:

As an important module in CMMB system, the performance of phase locked loop will directly determines the accuracy, purity and synchronization of system clock. In this paper, a high performance CPPLL circuit is designed to make each system clock of base station to get strict synchronization in frequency and phase. Test results show that the performance of this design meets the CMMB system requirements

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Periodical:

Applied Mechanics and Materials (Volumes 556-562)

Pages:

1597-1600

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.556-562.1597

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Online since:

May 2014

Authors:

Xiao Wang*, Zhi Bin Zeng

Keywords:

Charge Pump, Clock Synchronization, Phase Frequency Detector, Phase Noise, PLL

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References

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