Design and Implementation of CRC Error Correction for ADS-B System Responding Based on FPGA

Yu Ping Ma; Jun Zhang

doi:10.4028/www.scientific.net/AMM.577.994

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 577Design and Implementation of CRC Error Correction...

Design and Implementation of CRC Error Correction for ADS-B System Responding Based on FPGA

Abstract:

Automatic Dependent Surveillance Broadcast (ADS-B) system signal error detection and correction process scheme are introduced in this paper, and the working principle of cyclic redundancy check (CRC) is described. Then, this paper provides an error correction algorithm based on the confidence judgment and an error correction process flow chart based on ADS-B system. Finally, the design of CRC checksum is performed by taking use of Verilog HDL, and the simulation and verification are achieved in Modelism software platform. Experimental results show that the algorithm can carry out verification and error correction for ADS-B responding signal and can improve the reliability of ADS-B system signal transmission.

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Periodical:

Applied Mechanics and Materials (Volume 577)

Pages:

994-997

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.577.994

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Online since:

July 2014

Authors:

Yu Ping Ma*, Jun Zhang

Keywords:

ADS-B, Confidence, CRC, Error Correction, FPGA

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* - Corresponding Author

References

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