Design of Structure of Debugging Software in CPU Based on JTAG

Ping Zhang; Zuo Cheng Xing

doi:10.4028/www.scientific.net/AMM.58-60.1866

Paper Titles

NSCT De-Noising Algorithm Based on Image Partition and Noise Variance Estimation
p.1842

Noise Classification Based on GMM and AANN
p.1847

Testing of Fabric Dynamic Moisture Transfer Based on Munsell Color HV/C Value
p.1854

Implementation of Heuristic Technique and Genetic Algorithms in Shikaku Puzzle Problem
p.1860

Design of Structure of Debugging Software in CPU Based on JTAG
p.1866

Enhanced Epipolar Constraint for Point Correspondence in Computer Vision System
p.1871

Edge Detection of IR Image via Chirplet Fractal Dimension
p.1877

Infrared Image Edge Detection of High Voltage Insulator Chain
p.1882

Design and Application of Frequency Conversion Constant Pressure Water Supply System
p.1886

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 58-60Design of Structure of Debugging Software in CPU...

Design of Structure of Debugging Software in CPU Based on JTAG

Abstract:

It is important to own the capability of debugging application and system software and multitasking system in the design of microprocessor at present. In this paper, we proposed a debugging structure based on JTAG port and combined with boundary-scan technology and interrupt system, which can allow users to debug software procedure by the debugger which is connected to JTAG port. It is easy to form a standardized structure and applicable to all general-purpose CPU and only increases the difficulty of the circuit logic design.

You might also be interested in these eBooks

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volumes 58-60)

Pages:

1866-1870

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.58-60.1866

Citation:

Cite this paper

Online since:

June 2011

Authors:

Ping Zhang, Zuo Cheng Xing

Keywords:

Boundary Scan, Debugging Software, Debugging Structure, Interrupt Handler, JTAG Port

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

References

[1] LI Shaoqing, DENG Qinxue, Integrated Design of the Fault Test Structure AND the Debugging Structure[J], computer engineering & science, 2006, 28(8): 99-103.

Google Scholar

[2] IEEE Std 1149. 1-2001, IEEE Standard Test Access Port and Boundary—Scan Architecture [S]. (2001).

DOI: 10.1109/ieeestd.1995.122623

Google Scholar

[3] ZHANG Yongguang, XU Yuanxin, WANG Kuang, Challenges for Progress in Test and Design for Testability[J], Semiconductor Technology, 2005, 30(2): 33-37.

Google Scholar

[4] GE Qing, etal, Design of PCI-1149. 1 Boundary-scan Master Controller[J], Journal of Electronic Measurement and Instrument, 2006，20（4）：69-72.

Google Scholar

[5] WANG xiaohui, Design of structural testability of digital systems[J], Foreign Electronic Measurement Technology, 2006, 25(4): 16-18.

Google Scholar

[6] Ping Zhang, Yanmin Song, Jianmin Zhang, and Zuocheng Xing, Design of Testing Struture in Microprocessor Based on JTAG[C], 2009 International Symposium on Computational Intelligence and Design, 2009, 1: 223-226.

DOI: 10.1109/iscid.2009.62

Google Scholar