The Design and Implementation of Fast-Path Architecture for IPv6 Control Router

Guang Wang

doi:10.4028/www.scientific.net/AMM.596.892

Paper Titles

A New Method for High Speed CAN Protocol Conversion Circuit
p.873

A NHPP-Based Reliability Model of Wireless Sensor Networks
p.877

Implementation of USB in Embedded Systems Based on ARM Microprocessor
p.883

The Network Security System Research Based on Intrusion Detection
p.888

The Design and Implementation of Fast-Path Architecture for IPv6 Control Router
p.892

A Pushlet System Optimization Method Based on Servlet
p.899

RETRACTED: A Refinement of Hierarchical Databases
p.903

Design and Implementation of University Parking Query System
p.909

SQL Server Access Methods Based on LabVIEW
p.914

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 596The Design and Implementation of Fast-Path...

The Design and Implementation of Fast-Path Architecture for IPv6 Control Router

Abstract:

In view of the difficulties of the current router architecture such as capacity, scalability, and power consumption, a fast-path architecture of IPv6 router suitable for parallel processing is proposed. The fast-path architecture of IPv6 router is designed and implemented using NoC structure. Thereby, a parallel processing structure of IP packets combining the distributed IP address lookup and the parallel IP packet switching is implemented. It is convenient to replace the search algorithm and to expand the hardware scale, and it can improve the overall performance of the router effectively.

You might also be interested in these eBooks

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volume 596)

Pages:

892-896

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.596.892

Citation:

Cite this paper

Online since:

July 2014

Authors:

Guang Wang*

Keywords:

IPv6 Router, NoC, Parallel Processing

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

* - Corresponding Author

References

[1] Chao H J, Liu B. High performance switches and routers. Wiley-Interscience, (2007).

Google Scholar

[2] Li Q, Jinmei T, Shima K. IPv6 Core Protocols Implementation (The Morgan Kaufmann Series in Networking). Morgan Kaufmann Publishers Inc. San Francisco, CA, USA, (2006).

Google Scholar

[3] Baker, F. Requirements for IP version 4 routers . RFC 1812, https: /tools. ietf. org/html/rfc1812. June (1995).

Google Scholar

[4] Knuth, D.E., The art of computer programming. Vol. 3, Sorting and Searching. 1973, Reading, MA: Addison-Wesley.

Google Scholar

[5] Lampson, B., V. Srinivasan and G. Varghese, IP lookups using multiway and multicolumn search. IEEE/ACM Transactions on Networking (TON), 1999. 7(3): pp.324-334.

DOI: 10.1109/90.779199

Google Scholar

[6] Minkenberg C. Current issues in packet switch design. ACM SigComm. Comput. Comm. Rev. Jan. 2003, 33(1).

DOI: 10.1145/774763.774782

Google Scholar

[7] W. Dally and B. Towles. Route packets, not wires: on-chip interconnection networks. Proc. the Design Automation Conference, Las Vegas, NV, 2001: 684-689.

DOI: 10.1109/dac.2001.935594

Google Scholar

[8] G. De Micheli and L. Benini, Eds. Networks on Chips: Technology and Tools. San Mateo, CA: Morgan Kaufmann, (2006).

Google Scholar

[9] J. Hu and R. Marculescu. Energy and performance aware mapping for regular NoC architectures. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 4, April 2005: 551-562.

DOI: 10.1109/tcad.2005.844106

Google Scholar