A Speculative Approach to Improve the Double Instruction Executions in the Embedded Chips

Abstract:

Diminutive devices of present and future microprocessor generations are drawing increased attentions for transient errors. To address reliability issues, fault tolerance mechanisms must be taken into consideration. In this paper, we involve Reliability Station (RS) into modern superscalar out-of-order data path. In our proposed mechanism, each instruction in the pipeline will be executed twice and the dual results are stored in RS before they can be used. The fault detection is completed by a comparison between the two results and the recovery is achieved by re-executed the corresponding instructions. The simulation results of 12 benchmarks chosen from spec2000 and mibench show that the performance loss of our solution ranges from 30.29% to 83.32% with an average of 54.90% compared to single instruction execution, which is lower than that of Double Instruction Execution (DIE) schemes with an average of 78.42%. Meanwhile, due to the high efficiency of the recovery, our mechanism will exhibit better performance and power efficiency than DIEs within high transient error rates.

• Periodical: Applied Mechanics and Materials (Volumes 635-637)
• Pages: 1072-1075
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.635-637.1072
• Online since: September 2014
• Authors: Xiang Zhi Lu, Hong Jun Dai*, Lei Ju
• Keywords: Double Instruction Execution, Fault Tolerance, Reliability Station, Transient Error

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