Practicability Discussion and Verification of Using FPGA to NAND Flash

Min Yang; Kai Xu; Xiang Fen Zhang

doi:10.4028/www.scientific.net/AMM.644-650.3655

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 644-650Practicability Discussion and Verification of...

Practicability Discussion and Verification of Using FPGA to NAND Flash

Abstract:

The practicability of applying FPGA to NAND Flash in two aspects: address management and bad block management, which is discussed and verified in this paper. Functions of these three aspects can be realized simultaneously, the reliability and running speed of NAND Flash will be greatly promoted.

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Periodical:

Applied Mechanics and Materials (Volumes 644-650)

Pages:

3655-3658

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.644-650.3655

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Cite this paper

Online since:

September 2014

Authors:

Min Yang*, Kai Xu, Xiang Fen Zhang

Keywords:

Address, Bad Block, ECC, FPGA, NAND Flash

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* - Corresponding Author

References

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