A 14-Bit Pipeline ADC Behavior Model Using Verilog-A for SOC

Wang Liao; Lang Cheng Lei; Xiao Dan Zhou

doi:10.4028/www.scientific.net/AMM.644-650.3663

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 644-650A 14-Bit Pipeline ADC Behavior Model Using...

A 14-Bit Pipeline ADC Behavior Model Using Verilog-A for SOC

Abstract:

This paper presents the advantage of behavior model. This is useful for the SOC fast verification. A 14 bit pipeline ADC is constructed with simulation of behavior model and the noise model. A comparison of result is illustrated, between the ideal 14 bit ADC behavior model and the 14 bit pipeline ADC with non-idealities.

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Periodical:

Applied Mechanics and Materials (Volumes 644-650)

Pages:

3663-3666

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.644-650.3663

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Cite this paper

Online since:

September 2014

Authors:

Wang Liao*, Lang Cheng Lei, Xiao Dan Zhou

Keywords:

Behavior Model, Non-Idealities, Pipeline ADC, SoC

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* - Corresponding Author

References

[1] FitzPat rick D , Miller I. Analog Behavioral Modeling With the Verilog-A Language[M] . Kluwer Academic Publishers , (2003).

Google Scholar

[2] Tony Chan Carusone, David A. Johns, Kenneth W. Martin. Analog Integrated Circuit Design[M]. John Wiley&Sons, Inc.

Google Scholar

[3] Shanthi Pavan, Rapid Simulation of Current Steering Digital-to-Analog Converters using Verilog-A. IEEE Custom Integrated Circuits Conference, 2006. 201-204.

DOI: 10.1109/cicc.2006.320910

Google Scholar

[4] Yi WANG, YiKai WANG, Lenian HE, Behavior Modeling for Operational Amplifier in Sigma-Delta Modulators with Verilog-A. IEEE, 2008. 1612-1615.

DOI: 10.1109/apccas.2008.4746344

Google Scholar

[5] CAI Wei-hua, GUO Yu-shun, Behavior simulation of pipeline ADC. Electronic Design Engineering, 2012. 110-112.

Google Scholar

[6] Cadence Verilog-A Language Reference, version5. 1, (2004).

Google Scholar

[7] Bibhu Datta Sahoo, Behzad Razazi. A fast simulator for pipelined A/Dconverters. IEEE, 2009. 402-406.

Google Scholar