Performance Evaluation of a Massively Parallel Decoder for CISC Microprocessors

Jian Feng An; Xiao Ya Fan; Jun Zhang; Hai Feng Yi

doi:10.4028/www.scientific.net/AMM.65.590

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 65Performance Evaluation of a Massively Parallel...

Performance Evaluation of a Massively Parallel Decoder for CISC Microprocessors

Abstract:

Performance of the decoder unit is critical for CISC microprocessors. To take x86 ISA for an example, we analyzes the x86 instruction formats in detail. We compare two decoding strategies used in Longteng C1&C2 microprocessors: One is a simply direct serial decoder; another is a massively parallel decoder. Simulation results show speedups around 2.2~3.6 are obtained by using 10 parallel sub-decoders.

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Periodical:

Applied Mechanics and Materials (Volume 65)

Pages:

590-594

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.65.590

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Online since:

June 2011

Authors:

Jian Feng An, Xiao Ya Fan, Jun Zhang, Hai Feng Yi

Keywords:

Decoder, Microprocessor, Performance Evaluation

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