Performance Evaluation of a Massively Parallel Decoder for CISC Microprocessors

Abstract:

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Performance of the decoder unit is critical for CISC microprocessors. To take x86 ISA for an example, we analyzes the x86 instruction formats in detail. We compare two decoding strategies used in Longteng C1&C2 microprocessors: One is a simply direct serial decoder; another is a massively parallel decoder. Simulation results show speedups around 2.2~3.6 are obtained by using 10 parallel sub-decoders.

Info:

Periodical:

Edited by:

Zhenyu Du and Bin Liu

Pages:

590-594

DOI:

10.4028/www.scientific.net/AMM.65.590

Citation:

J. F. An et al., "Performance Evaluation of a Massively Parallel Decoder for CISC Microprocessors", Applied Mechanics and Materials, Vol. 65, pp. 590-594, 2011

Online since:

June 2011

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Price:

$35.00

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