The Design and Implementation of a Heterogeneous Multi-Core Security Chip Architecture Based on Shared Memory System

Abstract:

With the existence of traditional SOC chip, the encryption and decryption speed and low power cannot meet the computing needs of the modern diversity, then we present a heterogeneous multi-core system which designed based on shared memory on the Xilinx Virtex-5 platform. This paper is in-depth research about heterogeneous multi-core password architecture, static task partitioning, scheduling strategy and the communication mechanism between cores. The three cores systems are designed and builded based on shared memory to realize ZUC algorithm which generates a stream cipher on virtex-5 platform. The three microblaze cores are responsible for inter-core communication, the implementation of ZUC algorithm and articulating IC card to read keys. Through the design of three cores system, give full play to the hardware, software and computer architecture parallelism at all levels to improve the performance of the algorithm to achieve high performance green computing.

• Periodical: Applied Mechanics and Materials (Volumes 668-669)
• Pages: 1314-1318
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.668-669.1314
• Online since: October 2014
• Authors: Lei Zhang*, Ren Ping Dong, Chang Zhang, Ya Ping Yu
• Keywords: Heterogeneous, IIC Communication, Multi-Core, Shared Memory, ZUC Algorithm

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