System on Chip Design for Multi-Principle of Relay Protection in the FPGA

Abstract:

To improve the reliability and integration of relay protection devices in power, the system on chip design for multi-principle of relay protection on FPGA is proposed. The data acquisition, digital signal processing, hardware protection algorithm, FPGA and MCU process scheduling, MCU and peripheral devices communication are designed, the hardware compilation model is set up by QuartusII on FPGA, and the simulation and experimental verification are performed. The results show that the proposed system can improve the speed of hardware protection and reduce the volume of the device, and has reconstruction on architecture.

• Periodical: Applied Mechanics and Materials (Volumes 668-669)
• Pages: 857-861
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.668-669.857
• Online since: October 2014
• Authors: Peng Fei Hu*, Yu Xiang Yuan, Zhi Juan Qu, Xue Ping Jiang
• Keywords: Digital Signal Processing, FPGA, Hardware Protection Algorithms, Process Scheduling, Relay Protection

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